A d v a n c e I n f o r m a t i o n
status bits. After a program or erase cycle has been completed, the device is
ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low V detector that automat-
CC
ically inhibits write operations during power transitions. The password and
software sector protection feature disables both program and erase opera-
tions in any combination of sectors of memory. This can be achieved in-system
at V level.
CC
The Program/Erase Suspend/Erase Resume feature enables the user to put
erase on hold for any period of time to read data from, or program data to, any
sector that is not selected for erasure. True background erase can thus be
achieved.
The hardware RESET# pin terminates any operation in progress and resets the
internal state machine to reading array data.
The device offers two power-saving features. When addresses have been stable
for a specified amount of time, the device enters the automatic sleep mode.
The system can also place the device into the standby mode. Power consump-
tion is greatly reduced in both these modes.
AMD’s Flash technology combines years of Flash memory manufacturing experi-
ence to produce the highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector simultaneously via
Fowler-Nordheim tunnelling. The data is programmed using hot electron
injection.
March 22, 2004 30606B0
S29CD032G
3
SPANSION [ SPANSION ]
