D a t a S h e e t ( P r e l i m i n a r y )
Table 8.4 S25FL040A Sector Address Table (Uniform Sectors)
Sector
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
Address Range
070000h
060000h
050000h
040000h
030000h
020000h
010000h
000000h
07FFFFh
06FFFFh
05FFFFh
04FFFFh
03FFFFh
02FFFFh
01FFFFh
00FFFFh
9. Command Definitions
The host system must shift all commands, addresses, and data in and out of the device, beginning with the
most significant bit. On the first rising edge of SCK after CS# is driven low, the device accepts the one-byte
command on SI (all commands are one byte long), most significant bit first. Each successive bit is latched on
the rising edge of SCK. Table 9.5 on page 24 lists the complete set of commands.
Every command sequence begins with a one-byte command code. The command may be followed by
address, data, both, or nothing, depending on the command. CS# must be driven high after the last bit of the
command sequence has been written.
The Read Data Bytes (READ), Read Status Register (RDSR), Read Data Bytes at Higher Speed
(FAST_READ) and Read Identification (RDID) command sequences are followed by a data output sequence
on SO. CS# can be driven high after any bit of the sequence is output to terminate the operation.
The Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable
(WREN), or Write Disable (WRDI) commands require that CS# be driven high at a byte boundary, otherwise
the command is not executed. Since a byte is composed of eight bits, CS# must therefore be driven high
when the number of clock pulses after CS# is driven low is an exact multiple of eight.
The device ignores any attempt to access the memory array during a Write Status Register, program, or
erase operation, and continues the operation uninterrupted.
9.1
Read Data Bytes (READ)
The Read Data Bytes (READ) command reads data from the memory array at the frequency (fSCK) presented
at the SCK input, with a maximum speed of 33 MHz. The host system must first select the device by driving
CS# low. The READ command is then written to SI, followed by a 3-byte address (A23-A0). Each bit is
latched on the rising edge of SCK. The memory array data, at that address, are output serially on SO at a
frequency fSCK, on the falling edge of SCK.
Figure 9.1 and Table 9.5 detail the READ command sequence. The first byte specified can be at any location.
The device automatically increments to the next higher address after each byte of data is output. The entire
memory array can therefore be read with a single READ command. When the highest address is reached, the
address counter reverts to 00000h, allowing the read sequence to continue indefinitely.
The READ command is terminated by driving CS# high at any time during data output. The device rejects any
READ command issued while it is executing a program, erase, or Write Status Register operation, and
continues the operation uninterrupted.
14
S25FL040A
S25FL040A_00_B0 August 31, 2006
SPANSION [ SPANSION ]
