D a t a S h e e t ( P r e l i m i n a r y )
Table 7.3 S25FL040A Protected Area Sizes (Uniform Sector)
Status Register
Block Protect Bits
Memory Array
Protected
BP2 BP1 BP0 Address Range
Protected
Sectors
Unprotected
Unprotected Protected Portion of
Address Range
Sectors
SA7:SA0
SA6:SA0
SA5:SA0
SA3:SA0
None
Total Memory Area
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None
(0)
00000–7FFFF
00000–6FFFF
00000–5FFFF
00000–3FFFF
None
0
70000–7FFFF
60000–7FFFF
40000–7FFFF
00000–7FFFF
00000–7FFFF
00000–7FFFF
00000–7FFFF
(1) SA7
Upper 1/8 (64 KB)
Lower 1/4 (128 KB)
Lower 1/2 (256 KB)
All (512 KB)
(2) SA7:SA6
(4) SA7:SA4
(8) SA7:SA0
(8) SA7:SA0
(8) SA7:SA0
(8) SA7:SA0
None
None
All (512 KB)
None
None
All (512 KB)
None
None
All (512 KB)
7.7
Hold Mode (HOLD#)
The Hold input (HOLD#) stops any serial communication with the device, but does not terminate any Write
Status Register, program or erase operation that is currently in progress.
The Hold mode starts on the falling edge of HOLD# if SCK is also low (see Figure 7.1, on page 12, standard
use). If the falling edge of HOLD# does not occur while SCK is low, the Hold mode begins after the next falling
edge of SCK (non-standard use).
The Hold mode ends on the rising edge of HOLD# signal (standard use) if SCK is also low. If the rising edge
of HOLD# does not occur while SCK is low, the Hold mode ends on the next falling edge of CLK (non-
standard use) See Figure 7.1.
The SO output is high impedance, and the SI and SCK inputs are ignored (don’t care) for the duration of the
Hold mode.
CS# must remain low for the entire duration of the Hold mode to ensure that the device internal logic remains
unchanged. If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the
device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high,
followed by driving CS# low.
Figure 7.1 Hold Mode Operation
SCK
HOLD#
Hold
Hold
Condition
Condition
(standard use)
(non-standard use)
12
S25FL040A
S25FL040A_00_B0 August 31, 2006