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AM29LV640MH112RPCI 参数 Datasheet PDF下载

AM29LV640MH112RPCI图片预览
型号: AM29LV640MH112RPCI
PDF下载: 下载PDF文件 查看货源
内容描述: 64兆位(4M ×16位/ 8的M× 8位)的MirrorBit 3.0伏特,只有统一部门快闪记忆体与VersatileI / O控制 [64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O Control]
分类和应用: 闪存内存集成电路
文件页数/大小: 62 页 / 1108 K
品牌: SPANSION [ SPANSION ]
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D A T A S H E E T  
Program Operation  
or Write-to-Buffer  
Sequence in Progress  
Write Program Suspend  
Command Sequence  
Write address/data  
XXXh/B0h  
Command is also valid for  
Erase-suspended-program  
operations  
Wait 15 μs  
Autoselect and SecSi Sector  
read operations are also allowed  
Read data as  
required  
Data cannot be read from erase- or  
program-suspended sectors  
Done  
No  
reading?  
Yes  
Write Program Resume  
Command Sequence  
Write address/data  
XXXh/30h  
Device reverts to  
operation prior to  
Program Suspend  
Figure 6. Program Suspend/Program Resume  
mediately terminates the erase operation. If that oc-  
curs, the chip erase command sequence should be  
reinitiated once the device has returned to reading  
array data, to ensure data integrity. Note that the  
SecSi Sector, autoselect, and CFI functions are un-  
available when an erase operation is in progress.  
Chip Erase Command Sequence  
Chip erase is a six bus cycle operation. The chip erase  
command sequence is initiated by writing two unlock  
cycles, followed by a set-up command. Two additional  
unlock write cycles are then followed by the chip erase  
command, which in turn invokes the Embedded Erase  
algorithm. The device does not require the system to  
preprogram prior to erase. The Embedded Erase algo-  
rithm automatically preprograms and verifies the entire  
memory for an all zero data pattern prior to electrical  
erase. The system is not required to provide any con-  
trols or timings during these operations. Tables 10 and  
11 show the address and data requirements for the  
chip erase command sequence.  
Figure 7 illustrates the algorithm for the erase opera-  
tion. Refer to the Erase and Program Operations ta-  
bles in the AC Characteristics section for parameters,  
and Figure 19 section for timing diagrams.  
Sector Erase Command Sequence  
Sector erase is a six bus cycle operation. The sector  
erase command sequence is initiated by writing two  
unlock cycles, followed by a set-up command. Two ad-  
ditional unlock cycles are written, and are then fol-  
lowed by the address of the sector to be erased, and  
the sector erase command. Tables 10 and 11 show the  
address and data requirements for the sector erase  
command sequence.  
When the Embedded Erase algorithm is complete, the  
device returns to the read mode and addresses are no  
longer latched. The system can determine the status  
of the erase operation by using DQ7, DQ6, or DQ2.  
Refer to the Write Operation Status section for infor-  
mation on these status bits.  
The device does not require the system to preprogram  
prior to erase. The Embedded Erase algorithm auto-  
matically programs and verifies the entire memory for  
Any commands written during the chip erase operation  
are ignored. However, note that a hardware reset im-  
30  
Am29LV640MH/L  
December 14, 2005