D A T A S H E E T
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
32 Kword
8 Kword
0.4
0.4
54
5
5
Sector Erase Time
s
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
s
µs
µs
s
Excludes system level
overhead (Note 5)
Word Programming Time
11.5
4
210
120
144
48
Accelerated Word Programming Time
Chip Programming Time (Note 3)
Excludes system level
overhead (Note 5)
48
16
Accelerated Chip Programming Time
s
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 1.8 V VCC, 1 million cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 1.8 V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 10 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1 million cycles.
DATA RETENTION
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
May 8, 2006 25692A2
Am29BDS643G
45
SPANSION [ SPANSION ]
