D A T A S H E E T
AC CHARACTERISTICS
Address wraps back to beginning of address group.
Initial Access
CLK
39
39
3A
3B
3C
3D
3E
3F
38
Address (hex)
A/DQ0:
A/DQ15
D0
D1
D2
D3
D4
D5
D6
D7
V
IH
AVD#
V
IL
V
IH
OE#,
CE#
V
IL
Note: 8-word linear burst mode shown. 16- and 32-word linear burst read modes behave similarly.
Figure 18. 8-, 16-, and 32-Word Linear Burst
Address Wrap Around
Address boundary occurs every 64 words, beginning at address
00003Eh: 00007Eh, 0000BEh, etc. Address 000000h is also a boundary crossing.
C59
C60
3C
C61
3D
C62
3E
C62
3E
C62
3E
C63
3F
C64
40
C65
41
C66
42
CLK
3B
Address (hex)
(stays high)
AVD#
RDY
tRACC
latency
A/DQ0:
A/DQ15
D59
D60
D61
D62
D63
D64
D65
D66
OE#,
CE#
(stays low)
Note: Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
Figure 19. Latency with Boundary Crossing (54 MHz and 66 MHz)
42
Am29BDS643G
25692A2 May 8, 2006
SPANSION [ SPANSION ]
