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AM29BDS643GT7GVAI 参数 Datasheet PDF下载

AM29BDS643GT7GVAI图片预览
型号: AM29BDS643GT7GVAI
PDF下载: 下载PDF文件 查看货源
内容描述: 64兆位(4M ×16位) CMOS 1.8伏只同步读/写,突发模式闪存 [64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory]
分类和应用: 闪存
文件页数/大小: 49 页 / 718 K
品牌: SPANSION [ SPANSION ]
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D A T A S H E E T  
See the following for additional information: Figure 4  
RDY: Ready  
(toggle bit flowchart), DQ6: Toggle Bit I (description),  
Figure 17 (toggle bit timing diagram), and Table 11  
(compares DQ2 and DQ6).  
The RDY is a dedicated output that indicates (when at  
logic low) the system should wait until RDY returns high  
before expecting the next word of data.  
RDY functions only while reading data in burst mode.  
The following conditions cause the RDY output to be  
low: during the initial access (in burst mode); after the  
boundary that occurs every 64 words beginning with  
the 63rd address, 3Eh; and when the clock frequency  
is less than 6 MHz (in which case RDY is low every third  
clock). The RDY pin will also switch during status reads  
if there is a clock signal at the CLK input. If RDY goes  
low, it indicates that the status data is not yet valid and  
that the system should wait until RDY returns high.  
START  
Read Byte  
(DQ0-DQ7)  
Address = VA  
Read Byte  
(DQ0-DQ7)  
Address = VA  
DQ6: Toggle Bit I  
Toggle Bit I on DQ6 indicates whether an Embedded  
Program or Erase algorithm is in progress or complete,  
or whether the device has entered the Erase Suspend  
mode. Toggle Bit I may be read at any address in the  
same bank, and is valid after the rising edge of the final  
WE# pulse in the command sequence (prior to the  
program or erase operation), and during the sector  
erase time-out.  
No  
DQ6 = Toggle?  
Yes  
No  
DQ5 = 1?  
During an Embedded Program or Erase algorithm  
operation, successive read cycles to any address  
cause DQ6 to toggle. Note that OE# must be low during  
toggle bit status reads. When the operation is com-  
plete, DQ6 stops toggling.  
Yes  
Read Byte Twice  
(DQ 0-DQ7)  
Adrdess = VA  
After an erase command sequence is written, if all  
sectors selected for erasing are protected, DQ6 toggles  
for approximately 100 µs, then returns to reading array  
data. If not all selected sectors are protected, the  
Embedded Erase algorithm erases the unprotected  
sectors, and ignores the selected sectors that are pro-  
tected.  
No  
DQ6 = Toggle?  
The system can use DQ6 and DQ2 together to deter-  
mine whether a sector is actively erasing or is  
erase-suspended. When the device is actively erasing  
(that is, the Embedded Erase algorithm is in progress),  
DQ6 toggles. When the device enters the Erase  
Suspend mode, DQ6 stops toggling. However, the  
system must also use DQ2 to determine which sectors  
are erasing or erase-suspended. Alternatively, the  
system can use DQ7 (see the subsection on DQ7:  
Data# Polling).  
Yes  
FAIL  
PASS  
Note: The system should recheck the toggle bit even if DQ5  
= “1” because the toggle bit may stop toggling as DQ5  
changes to “1.See the subsections on DQ6 and DQ2 for  
more information.  
If a program address falls within a protected sector,  
DQ6 toggles for approximately 1 μs after the program  
command sequence is written, then returns to reading  
array data.  
Figure 4. Toggle Bit Algorithm  
DQ6 also toggles during the erase-suspend-program  
mode, and stops toggling once the Embedded  
Program algorithm is complete.  
May 8, 2006 25692A2  
Am29BDS643G  
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