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AM29BDS643GT7GVAI 参数 Datasheet PDF下载

AM29BDS643GT7GVAI图片预览
型号: AM29BDS643GT7GVAI
PDF下载: 下载PDF文件 查看货源
内容描述: 64兆位(4M ×16位) CMOS 1.8伏只同步读/写,突发模式闪存 [64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory]
分类和应用: 闪存
文件页数/大小: 49 页 / 718 K
品牌: SPANSION [ SPANSION ]
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D A T A S H E E T  
WRITE OPERATION STATUS  
The device provides several bits to determine the status of a  
program or erase operation: DQ2, DQ3, DQ5, DQ6, and  
DQ7. Table 12 and the following subsections describe the  
function of these bits. DQ7 and DQ6 each offers a method  
for determining whether a program or erase operation is  
complete or in progress.  
invalid. Valid data on DQ0–DQ7 will appear on succes-  
sive read cycles.  
Table 12 shows the outputs for Data# Polling on DQ7.  
Figure 3 shows the Data# Polling algorithm. Figure 16  
in the AC Characteristics section shows the Data#  
Polling timing diagram.  
DQ7: Data# Polling  
The Data# Polling bit, DQ7, indicates to the host  
system whether an Embedded Program or Erase algo-  
rithm is in progress or completed, or whether a bank is  
in Erase Suspend. Data# Polling is valid after the rising  
edge of the final WE# pulse in the command sequence.  
START  
Read DQ7–DQ0  
Addr = VA  
During the Embedded Program algorithm, the device  
outputs on DQ7 the complement of the datum pro-  
grammed to DQ7. This DQ7 status also applies to pro-  
gramming during Erase Suspend. When the  
Embedded Program algorithm is complete, the device  
outputs the datum programmed to DQ7. The system  
must provide the program address to read valid status  
information on DQ7. If a program address falls within a  
protected sector, Data# Polling on DQ7 is active for  
approximately 1 µs, then that bank returns to the read  
mode.  
Yes  
DQ7 = Data?  
No  
No  
DQ5 = 1?  
During the Embedded Erase algorithm, Data# Polling  
produces a “0” on DQ7. When the Embedded Erase  
algorithm is complete, or if the bank enters the Erase  
Suspend mode, Data# Polling produces a “1” on DQ7.  
The system must provide an address within any of the  
sectors selected for erasure to read valid status infor-  
mation on DQ7.  
Yes  
Read DQ7–DQ0  
Addr = VA  
After an erase command sequence is written, if all  
sectors selected for erasing are protected, Data#  
Polling on DQ7 is active for approximately 100 µs, then  
the bank returns to the read mode. If not all selected  
sectors are protected, the Embedded Erase algorithm  
erases the unprotected sectors, and ignores the  
selected sectors that are protected. However, if the  
system reads DQ7 at an address within a protected  
sector, the status may not be valid.  
Yes  
DQ7 = Data?  
No  
PASS  
FAIL  
Notes:  
Just prior to the completion of an Embedded Program  
or Erase operation, DQ7 may change asynchronously  
with DQ0–DQ6 while Output Enable (OE#) is asserted  
low. That is, the device may change from providing  
status information to valid data on DQ7. Depending on  
when the system samples the DQ7 output, it may read  
the status or valid data. Even if the device has com-  
pleted the program or erase operation and DQ7 has  
valid data, the data outputs on DQ0–DQ6 may be still  
1. VA = Valid address for programming. During a sector  
erase operation, a valid address is any sector address  
within the sector being erased. During chip erase, a valid  
address is any non-protected sector address.  
2. DQ7 should be rechecked even if DQ5 = “1” because  
DQ7 may change simultaneously with DQ5.  
Figure 3. Data# Polling Algorithm  
26  
Am29BDS643G  
25692A2 May 8, 2006