D A T A S H E E T
Table 10. Command Definitions
Bus Cycles (Notes 2–5)
Third Fourth
Addr Data
First
Second
Fifth
Sixth
Command Sequence
(Note 1)
Addr Data Addr Data
Addr
Data
Addr Data Addr Data
Asynchronous Read (Note 6)
Reset (Note 7)
1
1
4
RA
XXX
555
RD
F0
Manufacturer ID
AA
2AA
2AA
55 (BA)555 90 (BA)X00
55 (BA)555 90 (BA)X01
0001
227E
(BA)
X0E
(BA)
X0F
Device ID
6
555
AA
2202
2200
Sector Lock Verify (Note 9)
4
4
555
555
AA
AA
2AA
2AA
55 (SA)555 90 (SA)X02 0000 0001
55 (BA)555 90 (BA)X03 0042 0043
Handshaking Option (Note 10)
Program
4
3
2
2
6
6
1
1
3
3
3
1
555
555
XXX
BA
AA
AA
A0
90
2AA
2AA
PA
55
55
PD
00
55
55
555
555
A0
20
PA
Data
Unlock Bypass
Unlock Bypass Program (Note 11)
Unlock Bypass Reset (Note 12)
Chip Erase
XXX
2AA
2AA
555
555
BA
AA
AA
B0
30
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Erase Suspend (Note 13)
Erase Resume (Note 14)
Sector Lock/Unlock
BA
XXX
555
555
55
60
XXX
2AA
2AA
60
SLA
60
Set Configuration Register (Note 15)
Enable PS Mode
AA
AA
98
55 (CR)555 C0
55 555 70
CFI Query (Note 16)
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse, whichever happens
later.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A21–A12 uniquely select any sector.
BA = Address of the bank (A21, A20) that is being switched to
autoselect mode, is in bypass mode, or is being erased.
SLA = Address of the sector to be locked. Set sector address (SA) and
either A6 = 1 for unlocked or A6 = 0 for locked.
CR = Configuration Register set by address bits A16–A12.
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# pulse, whichever happens first.
Notes:
1. See Table 1 for description of bus operations.
10. The data is 0043h for handshaking enabled.
2. All values are in hexadecimal.
11. The Unlock Bypass command sequence is required prior to this
command sequence.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
12. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass mode.
4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
13. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
5. Unless otherwise noted, address bits A21–A12 are don’t cares.
6. No unlock or command cycles required when bank is reading
array data.
14. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
7. The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information).
15. The addresses in the third cycle must contain, on A12–A16, the
additional wait counts to be set. See “Set Configuration Register
Command Sequence”.
8. The fourth cycle of the autoselect command sequence is a read
cycle. The system must read device IDs across the 4th, 5th, and
6th cycles, The system must provide the bank address. See the
Autoselect Command Sequence section for more information.
16. Command is valid when device is ready to read array data or
when device is in autoselect moe.
9. The data is 0000h for an unlocked sector and 0001h for a locked
sector
May 8, 2006 25692A2
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SPANSION [ SPANSION ]
