P r e l i m i n a r y I n f o r m a t i o n
AC Characteristics
Program Command Sequence (last two cycles)
tAVCH
Read Status Data
CLK
tAS
tAH
AVD#
tAVDP
Addresses
555h
PA
VA
VA
In
Data
Complete
A0h
PD
tDS
tDH
Progress
tCAS
CE#f
tCH
OE#
WE#
tCSW
tWP
tWHWH1
tWPH
tWC
tVCS
VCC
f
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. Amax–A12 are don’t care during command sequence unlock cycles.
4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.
5. Either CE# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register.
The Configuration Register must be set to the Synchronous Read Mode.
Figure 37. Synchronous Program Operation Timings: CLK Latched Addresses
72
Am29BDS128H/Am29BDS064H
27024_A5_00_E June 18, 2004
SPANSION [ SPANSION ]
