P r e l i m i n a r y I n f o r m a t i o n
AC Characteristics
Program Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
V
IL
tAVSW
tAVHW
AVD#
tAVDP
tAS
tAH
Addresses
Data
555h
PA
VA
VA
In
A0h
Complete
PD
Progress
tDS
tDH
CE#f
tCH
OE#
WE#
tWP
tWHWH1
tCS
tWPH
tWC
tVCS
V
CCf
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. Amax–A12 are don’t care during command sequence unlock cycles.
4. CLK can be either VIL or VIH
.
5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Reg-
ister.
Figure 35. Asynchronous Program Operation Timings: WE# Latched Addresses
70
Am29BDS128H/Am29BDS064H
27024_A5_00_E June 18, 2004
SPANSION [ SPANSION ]
