P r e l i m i n a r y I n f o r m a t i o n
AC Characteristics
AVD#
tCEZ
tCE
CE#
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
VA
Addresses
Data
VA
Status Data
Status Data
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm
operation is complete, and Data# Polling will output true data.
3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.
Figure 40. Data# Polling Timings (During Embedded Algorithm)
AVD#
tCEZ
tCE
CE#
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
Addresses
Data
VA
VA
Status Data
Status Data
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm
operation is complete, the toggle bits will stop toggling.
3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.
Figure 41. Toggle Bit Timings (During Embedded Algorithm)
June 18, 2004 27024_A5_00_E
Am29BDS128H/Am29BDS064H
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SPANSION [ SPANSION ]
