P r e l i m i n a r y I n f o r m a t i o n
AC Characteristics
Erase/Program Operations
Parameter
JEDEC
Standard
Description
Write Cycle Time (Note 1)
75 MHz
66 MHz
54 MHz
Unit
t
t
Min
Min
45
50
55
5
ns
AVAV
WC
Synchronous
Asynchronous
Synchronous
Asynchronous
4
Address Setup Time
t
t
ns
ns
AVWL
AS
(Notes 2, 3)
0
6
5.5
15
7
Address Hold Time
(Notes 2, 3)
t
t
Min
WLAX
AH
20
20
12
t
AVD# Low Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
10
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
AVDP
t
t
Data Setup Time
Data Hold Time
45
DVWH
DS
t
t
0
0
0
0
WHDX
DH
t
t
Read Recovery Time Before Write
CE# Setup Time to AVD#
GHWL
GHWL
t
CAS
t
t
CE# Hold Time
WHEH
CH
t
t
Write Pulse Width
20
30
20
WLWH
WP
t
t
Write Pulse Width High
15
20
0
WHWL
WPH
t
Latency Between Read and Write Operations
Programming Operation (Note 4)
SR/W
t
t
9
WHWH1
WHWH1
t
t
Accelerated Programming Operation (Note 4)
Sector Erase Operation (Notes 4, 5)
Chip Erase Operation (Notes 4, 5)
4
WHWH1
WHWH1
0.2
104
500
t
t
Typ
sec
WHWH2
WHWH2
t
V
Rise and Fall Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
VID
ACC
t
V
Setup Time (During Accelerated Programming)
1
50
0
VIDS
ACC
t
V
Setup Time
CC
VCS
t
t
CE# Setup Time to WE#
AVD# Setup Time to WE#
ELWL
CS
t
4
4
4
5
5
5
7
5
AVSW
t
AVD# Hold Time to WE#
AVHW
t
Address Setup Time to CLK (Notes 2, 3)
Address Hold Time to CLK (Notes 2, 3)
AVD# Hold Time to CLK
ACS
t
5.5
6
5
ACH
t
4
AVHC
t
Clock Setup Time to WE#
CSW
Notes:
1. Not 100% tested.
2. Asynchronous mode allows both Asynchronous and Synchronous program operation. Synchronous mode allows both
Asynchronous and Synchronous program operation.
3. In asynchronous program operation timing, addresses are latched on the falling edge of WE# or rising edge of AVD#. In
synchronous program operation timing, addresses are latched on the first of either the falling edge of WE# or the active
edge of CLK.
4. See the “Erase and Programming Performance” section for more information.
5. Does not include the preprogramming time.
68
Am29BDS128H/Am29BDS064H
27024_A5_00_E June 18, 2004