A D V A N C E
I N F O R M A T I O N
INPUT/OUTPUT DESCRIPTIONS
A21-A0
=
Address inputs
Data input/output
Chip Enable input. Asynchronous
relative to CLK for the Burst mode.
Output Enable input. Asynchronous
relative to CLK for the Burst mode.
Write Enable input.
Device Power Supply
(1.65 – 1.95 V).
Input & Output Buffer Power Supply
(either 1.6.5 – 1.95 V or 2.7 – 3.15 V).
Ground
Output Buffer Ground
No Connect; not connected internally
Ready output; indicates the status of
the Burst read. Low = data not valid at
expected time. High = data valid.
CLK is not required in asynchronous
mode. In burst mode, after the initial
word is output, subsequent active
edges of CLK increment the internal
address counter.
ACC
=
WP#
=
RESET#
=
AVD#
=
DQ15-DQ0 =
CE#
OE#
WE#
V
CC
V
IO
V
SS
V
SSIO
NC
RDY
=
=
=
=
=
=
=
=
=
Address Valid input. Indicates to
device that the valid address is
present on the address inputs
(A21–A0).
Low = for asynchronous mode,
indicates valid address; for burst
mode, causes starting address to be
latched.
High = device ignores address inputs
Hardware reset input. Low = device
resets and returns to reading array
data
Hardware write protect input. At V
IL
,
disables program and erase functions
in the two outermost sectors. Should
be at V
IH
for all other conditions.
At V
ID
, accelerates programming;
automatically places device in unlock
bypass mode. At V
IL
, locks all sectors.
Should be at V
IH
for all other
conditions.
CLK
=
LOGIC SYMBOL
22
A21–A0
CLK
WP#
ACC
CE#
OE#
WE#
RESET#
AVD#
RDY
DQ15–DQ0
16
8
Am29BDS640G
May 9, 2002
SPANSION [ SPANSION ]
