A D V A N C E I N F O R M A T I O N
The internal state machine is set for reading array data
If the host system crosses the bank boundary while
reading in burst mode, and the device is not program-
ming or erasing, a two-cycle latency will occur as
described above in the subsequent bank. If the host
system crosses the bank boundary while the device is
programming or erasing, the device will provide read
status information. The clock will be ignored. After the
host has completed status reads, or the device has
completed the program or erase operation, the host
can restart a burst operation using a new address and
AVD# pulse.
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition.
Requirements for Synchronous (Burst)
Read Operation
The device is capable of continuous sequential burst
operation and linear burst operation of a preset length.
When the device first powers up, it is enabled for asyn-
chronous read operation.
If the clock frequency is less than 6 MHz during a burst
mode operation, additional latencies will occur. RDY
indicates the length of the latency by pulsing low.
Prior to entering burst mode, the system should deter-
mine how many wait states are desired for the initial
word (tIACC) of each burst access, what mode of burst
operation is desired, which edge of the clock will be the
active clock edge, and how the RDY signal will transi-
tion with valid data. The system would then write the
burst mode configuration register command sequence.
See “Set Burst Mode Configuration Register Command
Sequence” and “Command Definitions” for further
details.
8-, 16-, and 32-Word Linear Burst with Wrap Around
The remaining three modes are of the linear wrap
around design, in which a fixed number of words are
read from consecutive addresses. In each of these
modes, the burst addresses read are determined by
the group within which the starting address falls. The
groups are sized according to the number of words
read in a single burst sequence for a given mode (see
Table 2.)
Once the system has written the “Set Burst Mode Con-
figuration Register” command sequence, the device is
enabled for synchronous reads only.
Table 2. Burst Address Groups
The initial word is output tIACC after the active edge of
the first CLK cycle. Subsequent words are output tBACC
after the active edge of each successive clock cycle,
which automatically increments the internal address
counter. Note that the device has a fixed internal
address boundary that occurs every 64 words, starting
at address 00003Fh. During the time the device is out-
putting data at this fixed internal address boundary
(address 00003Fh, 00007Fh, 0000BFh, etc.), a two
cycle latency occurs before data appears for the next
address (address 000040h, 000080h, 0000C0h, etc.).
The RDY output indicates this condition to the system
by pulsing low. For non-handshaking devices, there is
no two cycle latency between 3Fh and 40h (or multiple
thereof). See Table 10.
Mode
8-word
16-word
32-word
Group Size Group Address Ranges
8 words
16 words
32 words
0-7h, 8-Fh, 10-17h, ...
0-Fh, 10-1Fh, 20-2Fh, ...
00-1Fh, 20-3Fh, 40-5Fh, ...
As an example: if the starting address in the 8-word
mode is 39h, the address range to be read would be
38-3Fh, and the burst sequence would be
39-3A-3B-3C-3D-3E-3F-38h-etc. The burst sequence
begins with the starting address written to the device,
but wraps back to the first address in the selected
group. In a similar fashion, the 16-word and 32-word
Linear Wrap modes begin their burst sequence on the
starting address written to the device, and then wrap
back to the first address in the selected address group.
Note that in these three burst read modes the
address pointer does not cross the boundary that
occurs every 64 words; thus, no wait states are
inserted (except during the initial access).
For handshaking devices, if the address latched is 3Dh
(or 64 multiple), an additional cycle latency occurs prior
to the initial access. If the address latched is 3Eh (or 64
multiple) two additional cycle latency occurs prior to the
initial access and the 2 cycle latency between 3Fh and
40h (or 64 multiple) will not occur. For 3Fh latched
addresses (or 64 multiple) three additional cycle
latency occurs prior to the initial access and the 2 cycle
latency between 3Fh and 40h (or 64 multiple) will not
occur.
The RDY pin indicates when data is valid on the bus.
The devices can wrap through a maximum of 128
words of data (8 words up to 16 times, 16 words up to
8 times, or 32 words up to 4 times) before requiring a
new synchronous access (latching of a new address).
The device will continue to output sequential burst
data, wrapping around to address 000000h after it
reaches the highest addressable memory location,
until the system drives CE# high, RESET# low, or
AVD# low in conjunction with a new address. See
Table 1, “Device Bus Operations,” on page 10.
Burst Mode Configuration Register
The device uses a configuration register to set the
various burst parameters: number of wait states, burst
May 9, 2002
Am29BDS640G
11
SPANSION [ SPANSION ]
