A D V A N C E I N F O R M A T I O N
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Device Bus Operations
CLK
(See
Operation
CE#
L
OE#
L
WE#
H
A21–0
Addr In
Addr In
Addr In
Addr In
HIGH Z
HIGH Z
DQ15–0 RESET# Note) AVD#
Asynchronous Read - Addresses Latched
Asynchronous Read - Addresses Steady State
Asynchronous Write
I/O
I/O
H
H
H
H
H
L
X
X
L
L
L
H
L
L
L
H
L
I/O
Synchronous Write
L
H
L
I/O
Standby (CE#)
H
X
X
X
HIGH Z
HIGH Z
X
X
X
X
Hardware Reset
X
X
Burst Read Operations
Load Starting Burst Address
L
L
X
L
H
H
Addr In
HIGH Z
X
H
H
Advance Burst to next address with appropriate
Data presented on the Data Bus
Burst
Data Out
H
Terminate current Burst read cycle
H
X
X
X
H
H
HIGH Z
HIGH Z
HIGH Z
HIGH Z
H
L
X
X
Terminate current Burst read cycle via RESET#
X
Terminate current Burst read cycle and start
new Burst read cycle
L
X
H
HIGH Z
I/O
H
Legend: L = Logic 0, H = Logic 1, X = Don’t Care, S = Stable Logic 0 or 1 but no transitions.
Note: Default active edge of CLK is the rising edge.
Enhanced VersatileIO™ (VIO) Control
Requirements for Asynchronous Read
Operation (Non-Burst)
The Enhanced VersatileIO (VIO) control allows the host
system to set the voltage levels that the device gener-
ates at its data outputs and the voltages tolerated at its
data and address inputs to the same voltage level that
is asserted on the VIO pin. The device is available with
either 1.65–1.95 or 2.7–3.15 VIO. This allows the
device to operate in 1.8 V or 3 V system environments
as required.
To read data from the memory array, the system must
first assert a valid address on A21–A0, while driving
AVD# and CE# to VIL. WE# should remain at VIH. The
rising edge of AVD# latches the address. The data will
appear on DQ15–DQ0. Since the memory array is
divided into four banks, each bank remains enabled for
read access until the command register contents are
altered.
For example, a VIO of 2.7 – 3.15 volts allows for I/O at
the 3 volt level, driving and receiving signals to and
from other 3 V devices on the same bus.
Address access time (tACC) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (tCE) is the delay from the stable
addresses and stable CE# to valid data at the outputs.
The output enable access time (tOE) is the delay from
the falling edge of OE# to valid data at the output.
10
Am29BDS640G
May 9, 2002
SPANSION [ SPANSION ]
