A D V A N C E I N F O R M A T I O N
Figure 21, Figure 23
REVISION SUMMARY
Added note to indicate AVD# must toggle during
command sequence unlock cycles. Added tCSW1 to
Figure 21.
Revision A (February 13, 2002)
Initial release.
Figure 22, Figure 24
Revision A+1 (February 19, 2002)
Automatic Sleep Mode
Added figures, which show different timings between
addresses, CLK, WE#, and AVD#.
Clarified description to indicate that sleep mode is acti-
vated when the first CLK edge occurs after tACC
.
Figure 25, Figure 27, Figure 28
Figure 20, Asynchronous Program Operation
Timings
Added note to indicate AVD# must toggle during data
reads.
Modified to show that CLK is don’t care prior to AVD#
going low, and that AVD# must not be low before CE#
transitions low.
Figure 30, Figure 31
Shifted address, clock, and data cycle counts up by
one.
Revision A+2 (February 27, 2002)
Revision A + 4 (July 26, 2002)
Table 1, Device Bus Operations
Figure 21, Asynchronous Program Operation
Timings
Changed Synchronous Write to rising edge of CLK.
Extended don’t care section of CLK to falling edge of
WE#.
Writing Commands/Command Sequences
Added CLK as part of the asynchronous write opera-
tion system drive.
Revision A+3 (May 9, 2002)
Requirements for Synchronous (Burst) Read
Operation
Added VCC and VIO Power-up and Power-down
Sequencing section.
Shifted address, clock, and data cycle references in
third paragraph up by one.
AC Characteristics
Table 4, System Interface String
Changed tCHW erase/program time from Min to Max.
Corrected data for address 23h.
Figure 20, Asynchronous Program Operation
Timings
Table 9, Initial Access Cycles vs. Frequency
Changed tCSW1 reference to WE# from AVD#.
Added table.
Figure 21, Alternate Asynchronous Program
Operation Timings
Autoselect Command Sequence
Added bottom boot device IDs to table.
Changed to show CLK low after tCHW time.
Table 13, Command Definitions
Added bottom boot device IDs to table.
RDY: Ready
Figure 22, Synchronous Program Operation
Timings
Removed tACH.
Corrected address boundary from 63rd word/3Eh to
64th word/3Fh.
Changed tAHW to tAVSW and added tCSW2.
Figure 23, Alternate Synchronous Program
Operation Timings
DC Characteristics
Added VIO = VIO min to test conditions for VOL and VOH
in table.
Changed tAVCH to tAVHC.
Removed tACH.
Erase/Program Operations table
DC Characteristics, CMOS Compatible
Added specifications for parameters tCSW1, tCSW2
tCHW, tAHC
,
Corrected ICCB OE# = VIL to = VIH; switched Typ. and
Max. values.
.
Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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Am29BDS640G
May 9, 2002
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