A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
CE#
CLK
AVD#
Addresses
OE#
VA
VA
tIACC
tIACC
Data
Status Data
Status Data
RDY
Notes:
1. The timings are similar to synchronous read timings.
3. RDY is active with data (A18 = 0 in the Burst Mode
Configuration Register). When A18 = 1 in the Burst Mode
Configuration Register, RDY is active one clock cycle before
data.
2. VA = Valid Address. Two read cycles are required to
determine status. When the Embedded Algorithm
operation is complete, the toggle bits will stop toggling.
4. AVD# must toggle between data reads.
Figure 29. Synchronous Data Polling Timings/Toggle Bit Timings
May 9, 2002
Am29BDS640G
55
SPANSION [ SPANSION ]
