CXD1968AR
QIC_MISC1
Read/Write
RESET: 0x0B
Default R/W
Offset Address: 0x62
Bit
Name
Description
7:4 Reserved
0
R/W
If set, enables the IQ phase imbalance (non-frequency
selective) detection/correction. This bit should be set when
using ZIF tuners to correct I/Q phase imbalance.
3
QIC ENABLE
1
R/W
Sets the loop gain value of the IQ phase imbalance corrector:
smaller values speed up the convergence rate.
QIC_GAIN Loop gain value
000
001
010
011
100
101
110
111
1/256
1/512
2:0 QIC_GAIN
011
R/W
1/1024
1/2048
1/4096
1/8192
1/16,384
1/32,768
QIC_IQPHASEERR
Read
0x00
Offset Address: 0x63
Bit
Name
Description
Default R/W
Detected IQ phase imbalance value.
7:0 IQPhaseErr
—
R
Phase imbalance (Degrees) = IQPhaseErr / 4
TRL_NOMINALRATE_0
Read/Write
Description
0x00
Offset Address: 0x65
Bit
Name
Default R/W
00 R/W
7:0 TRL Nominal Rate Bits 7:0 of TRL nominal rate
Note) 1. The TRL_NOMINALRATE is a 24-bit non-contiguous register comprising three 8-bit registers
called TRL_NOMINALRATE_2, TRL_NOMINALRATE_1 and TRL_NOMINALRATE_0.
2. Also see TRL_NOMINALRATE_1 at address 0x1B and TRL_NOMINALRATE_2 at address
0x1C.
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SONY [ SONY CORPORATION ]
