欢迎访问ic37.com |
会员登录 免费注册
发布采购

CXD1968AR 参数 Datasheet PDF下载

CXD1968AR图片预览
型号: CXD1968AR
PDF下载: 下载PDF文件 查看货源
内容描述: DVB -T解调器 [DVB-T Demodulator]
分类和应用:
文件页数/大小: 97 页 / 746 K
品牌: SONY [ SONY CORPORATION ]
 浏览型号CXD1968AR的Datasheet PDF文件第68页浏览型号CXD1968AR的Datasheet PDF文件第69页浏览型号CXD1968AR的Datasheet PDF文件第70页浏览型号CXD1968AR的Datasheet PDF文件第71页浏览型号CXD1968AR的Datasheet PDF文件第73页浏览型号CXD1968AR的Datasheet PDF文件第74页浏览型号CXD1968AR的Datasheet PDF文件第75页浏览型号CXD1968AR的Datasheet PDF文件第76页  
CXD1968AR  
AGC_MINGAIN  
Read/Write  
RESET: 0x80  
Default R/W  
Offset Address: 0x55  
Bit  
Name  
Description  
AGC minimum gain. Sets a minimum gain limit for the IFAGC  
output. This register is a signed 8-bit value which sets the  
minimum gain according to the table below.  
7:0 AGCMINGAIN  
80h  
R/W  
Note) 1. MinGain is the minimum gain limit required at the IFAGC output, scaled to a 12-bit or 10-bit  
signed value depending upon the AGC resolution set in the AGC_PWM_ENH_CTL register.  
AGC resolution (bits)  
AGC_CTL (AGC_NEG) AGCMINGAIN  
12  
12  
10  
10  
0
1
0
1
MinGain / 16  
–MinGain / 16  
MinGain / 4  
–MinGain / 4  
Example using 12-bit AGC with positive gain polarity:  
Where the IFAGC output gain range is from –2048 (low gain) to +2047 (high gain) in 12-bit AGC  
mode with AGC_CTL (AGC_NEG) = 0, and the minimum gain is to be limited to -1024.  
AGCMINGAIN = –1024/16 = –64  
Example using 10-bit AGC with negative gain polarity:  
Where the IFAGC output gain range is from +512 (low gain) to –512 (high gain) in 10-bit AGC  
mode with AGC_CTL (AGC_NEG) = 1, and the minimum gain is to be limited to 256.  
AGCMINGAIN = –256/4 = –64  
2. The default value of –128 is compatible with the CXD1973Q giving full AGC gain range with no  
limiting.  
AGC_MODIFIED_TARGET_I  
Offset Address: 0x56  
Read Only  
Bit  
Name  
Description  
Default R/W  
When the AGC is “not locked”, this register will read back the  
user requested AGC target value as set in the AGC_TARGET  
register.  
AGC_MODIFIED_ When the AGC is “locked” (and the AGC_ENHANCED_ENABLE  
7:0  
R
TARGET_I  
bit is set active high in the AGC_PWM_ENH_CTL register),  
this register will contain the top 8 MSBs of the internally  
modified AGC target value as dictated by the I channel  
conditions.  
- 72 -  
 复制成功!