CXD1968AR
I2C Interface
SDA
(17)
(18)
SCL
(18)
S
(19)
P
(24)
P
(20)
(22)
(21)
(23)
Sr
(0°C < Ta < 70°C, AVSS = 0V, DVSS = 0V, CVSS = 0V, 3.15V ≤ AVDD ≤ 3.45V, 3.15V ≤ DVDD ≤ 3.45V, 3.15V
≤ CVDD ≤ 3.45V)
Item
Symbol
(16)
Condition
Min.
0
Typ.
Max.
400
Unit
kHz
fSCL,
SCL clock frequency
tSDABUF,
Bus free time between a STOP(P) and
START(S) condition
(17)
(18)
1.3
0.6
μs
μs
tSTAHD,
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tSCLLOW,
Low period of SCL clock
(19)
(20)
(21)
(22)
(23)
(24)
1.3
0.6
0.6
0
μs
μs
μs
μs
ns
μs
tSCLHIGH,
High period of SCL clock
tSTASU,
Setup time for a repeated START condition
tSDAHD,
SDA data hold time
0.9
tSDASU,
SDA data setup time
100
0.6
tSTOSU,
Setup time for STOP condition
- 40 -
SONY [ SONY CORPORATION ]
