CXD1199AQ
3-2. Read registers
3-2-1. HSTS (host status) register
bit 7 : BUSYSTS (busy status)
This is high when the host writes a command into the command register and low when the sub
CPU sets the CLRBUSY bit (bit 6) of the CLRCTL register.
bit 6 : DRQSTS (data request status)
Indicates to the host that the buffer memory data transfer request status is established. When
transferring data in the I/O mode, the host should confirm that this bit is high before accessing the
WRDATA or RDDATA register.
bit 5 : RSLRRDY (result read ready)
The result register is not empty when this bit is high. At this time, the host can read the result
register.
bit 4 : PRMWRDY (parameter write ready)
The PARAMETER register is not full when this bit is high. At this time, the host writes data into the
PARAMETER register.
bit 3 : PRMEMPT (parameter empty)
The PARAMETER register is empty when this bit is high.
bit 2 : ADPBUSY (ADPCM busy)
This bit is set high for ADPCM decoding.
bits 1, 0 :
RA1, 0
The values of the RA1 and 0 bits for the ADDRESS register can be read from these bits.
3-2-2. RESULT register
The host reads the results of the command execution through this register. The register has ah 8-byte FIFO
configuration.
3-2-3. RDDATA (read data) register
This register is where the data from the buffer memory is written from the host. Data can be read in the I/O
mode or using DMAC. The register has a 2-byte FIFO configuration.
3-2-4. HINTMSK (host interrupt mask) register
The values written in the HINTMSK register can be read from this register.
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