CXD1199AQ
4. Host DMA cycle
(1) Read
HDRQ
XHAC
Tdar
Tdad
Thrd1
XHRD
Thac
Tsac
HD7 to 0, P
Thdrd2
Thfrd2
Item
Symbol
Tdad
Min.
Typ.
Max.
Unit
HDRQ fall time (for XHAC ↓)
HDRQ rise time (for XHAC ↑)
XHAC setup time (for XHRD ↓)
XHAC hold time (for XHRD ↑)
Data delay time (for XHRD ↓)
Data float time (for XHRD ↑)
Low level XHRD pulse width
45 (70)
45 (70)
ns
ns
ns
ns
ns
ns
ns
Tdar
Tsac
5 (20)
0 (20)
Thac
Thdrd2
Thfrd2
60 (100)
15 (25)
0
Thrd1 100 (150)
(2) Write
HDRQ
Tdar
Tdad
XHAC
Thww1
XHWR
Thac
Tsac
HD7 to 0, P
Thswd2
Thhwd2
Item
Symbol
Tdad
Tdar
Min.
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
HDRQ fall time (for XHAC ↓)
HDRQ rise time (for XHAC ↑)
45 (70)
45 (70)
XHAC setup time (for XHWR ↓)
XHAC hold time (for XHWR ↑)
Data setup time (for XHWR ↓)
Data hold time (for XHWR ↑)
Low level XHWR pulse width
Tsac
5 (20)
0 (20)
Thac
Thswd2 40 (70)
Thhwd2 10 (30)
Thww1 60 (100)
—12—
SONY [ SONY CORPORATION ]
