CXA2108AQ
Reference
Pin
No.
Symbol
RDY
Equivalent circuit
Description
I/O voltage
level
READY signal output.
This indicates the drive current data
RAM access enabled period. Access
is enabled while high level is output.
(See the Timing Charts.)
13
14
O
O
CMOS
DLDI signal output.
This outputs the DLDI signal
synchronized with CLK.
DLDO
CMOS
Write ALL signal output.
One pulse (= high level signal with a
width of 1 clock) is output
synchronized with the rising edge of
1
the next CLK after the final address
of the currently selected mode is input.
Note that both the final address must
be input and the XCS and XWR input
levels must be low at the rising edge
of this CLK.
15
CMOS
O
WALL
DVCC
(See the Timing Charts for details.)
1
02Fh (Upper/Lower mode)
13 14 15
08Fh (Upper/Lower/RGB mode)
16 17 18
19 20 52
Upper signal output.
This is used as the LED switching signal.
(See the Timing Charts and Application
Circuits for details.)
16
17
18
XUPR
TEST_O
XB
O
O
O
CMOS
CMOS
CMOS
DGND
Test signal output.
This pin is unrelated to the functions of this IC.
Do not connect anything; leave this pin open.
Blue signal output.
This is used as the LED switching signal.
(See the Timing Charts and Application
Circuits for details.)
Red signal output.
This is used as the LED switching signal.
(See the Timing Charts and Application
Circuits for details.)
CMOS
CMOS
CMOS
19
20
52
XR
O
O
O
Green signal output.
This is used as the LED switching signal.
(See the Timing Charts and Application
Circuits for details.)
XG
Thermal Alarm Out signal output.
This pin normally outputs high level, but it
outputs low level when the internal
XTAO
temperature rises to an abnormally high level.
– 6 –
SONY [ SONY CORPORATION ]
