CXA2101AQ
CLP
HP-IN
In this way, the replacement
pulse is generated from the
HP input signal rise to the
CLP pulse fall.
Replacement pulse
Fig. 2. Replacement timing pulse for adjusting color difference input offset
Notes on Operation
• Since the RGB signals which are output from the CXA2101AQ are DC direct connected, the board pattern
must be designed with consideration given to minimizing interference from around the power supply and
GND. It is best to use a solid earth rather than separating the GND patterns for each pin. Design the power
supply to achieve an impedance as low as possible. Locate the bypass capacitor between the power supply
and GND as close to the pins as possible.
It is also recommended that a buffer be connected to RGBOUT as near to this IC as possible.
• Input the waveforms to SCP-IN (Pin 31) with the pulse widths (T1, T2) mentioned in the description of
operation regardless of the scanning frequency. This is to prevent the AKB timing generator from
malfunctioning.
• Input the Y, Cb, Cr, H and V signals at a sufficiently low impedance. This is particularly important for inputs to
the pins which are clamped (refer to the Pin Description).
• Use resistors (such as metal film resistors) with an error of less than 1% as the resistors which are connected
to IREF-SYNC (Pin 27) and IREF-YC (Pin 71).
• Processing of unused pins
Open: Pins 1 to 5, 7 to 11, 13 to 17, 19 to 23, 26, 45 and 49
Connect to GND: Pins 32, 33, 41 and 61
Connect to Vcc: Pins 46 to 48, 50 to 52, 62 to 64
Alternatively, the input pins for clamping (refer to the Pin Description) can be connected to GND via a
capacitor.
– 32 –
SONY [ SONY CORPORATION ]
