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CXA1734S 参数 Datasheet PDF下载

CXA1734S图片预览
型号: CXA1734S
PDF下载: 下载PDF文件 查看货源
内容描述: 美国音频多路复用解码器 [US Audio Multiplexing Decoder]
分类和应用: 解码器
文件页数/大小: 30 页 / 472 K
品牌: SONY [ SONY CORPORATION ]
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CXA1734S  
(1) L + R (MAIN)  
After the audio multiplexing signal input from COMPIN (Pin 11) passes through MVCA, the SAP signal  
and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the  
L - R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened  
(de-emphasized) and input to the matrix.  
(2) L - R (SUB)  
The L - R signal follows the same course as L + R before the pilot signal is canceled. L - R has no  
carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM  
modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave)  
to be used for the demodulation of the L - R signal. In the last stage, the residual high frequency  
components are removed by SUB LPF and the L - R signal is input to the dbx-TV block via the NRSW  
circuit after passing through SUBVCA.  
(3) SAP  
SAP is an FM signal using 5fH as a carrier as shown in the Fig.1. First, the SAP signal only is  
extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency  
components are removed and freqency characteristics flattened using SAP LPF, and the SAP signal is  
input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 18 output is soft  
muted.  
(4) Mode discrimination  
Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is  
performed by detecting the 5fH carrier amplitude. NOISE discrimination is performed by detecting the  
noise near 25 kHz after FM detection.  
(5) dbx-TV block  
Either the SAP signal or L - R signal input respectively from ST IN (Pin 14) or SAP IN (Pin 19) is  
selected by the mode control and input to the dbx-TV block.  
The input signal then passes through the fixed de-emphasis circuit and is applied to the variable de-  
emphasis circuit. The signal output from the variable de-emphasis circuit passes through an external  
capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a  
current to a voltage using an operational amplifier and then input to the matrix.  
The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by each of  
effective value detection circuits. Each of the effective value detection circuits passes the input signal  
through a predetermined filter for weighting before the effective value of the weighted signal is  
detected to provide the control signal.  
(6) Others  
“MVCA” is a VCA which adjusts the input signal level to the standard level of this IC. In addition, the  
input signal enters the decoder without passing through MVCA by setting to ATTSW = 1.  
The signals (L + R, L - R, SAP) input to “MATRIX” are selected according to the BUS data and  
whether there is ST or SAP discrimination, and any one of the ST-L, ST-R, MONO or SAP signals is  
output to LOUT and ROUT.  
“Bias” supplies the reference voltage and reference current to the other blocks. The currents flowing to  
the resistors connecting IREF (Pin 6) and ITIME (Pin 27) with GND become the reference current.  
—18—  
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