CXA1734S
Adjustment Method
1
2
3
ATT adjustment
1. TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”.
2. Input a 100 Hz, 245 mVrms sine wave signal to COMPIN and monitor the LOUT output level. Then,
adjust the “ATT” data for ATT adjustment so that LOUT output goes to the standard value.
3. Adjustment range:
Adjustment bits:
±30%
4 bits
Stereo VCO adjustment
1. TEST BIT is set to “TEST1 = 0” and “TEST-DA = 1”.
2. Monitor the ROUT output (4 fH free run) frequency in a no input state, and adjust “STVCO” adjustment
data so that this frequency is as close to 4fH (62.936 kHz) as possible.
3. Adjustment range:
Adjustment bits:
±20%
6 bits
SAPVCO adjustment
1. TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”.
2. Input a 5fH (SAP carrier , 78.67 kHz) , 147 mVrms sine wave signal to COMPIN. While monitoring the
STATUS FLAG (STA7, STA8) condition, adjust “SAPVCO” adjustment data.
3. Adjustment range:
Adjustment bits:
±20%
4 bits
Align SAPVCO with the center of the STA7 = 0 and STA8 = 1 (adjustment OK) condition range.
Adjustment point
Control data
"SAPVCO"
0
F
1
0
Measurement data
STA7 "SAPVCO1"
1
0
STA8 "SAPVCO2"
4
Stereo block dbx filter adjustment
1. TEST BIT is set to “TEST1 = 1” and “TEST-DA = 0”.
2. Input a 9.4 kHz, 600 mVrms sine wave signal to COMPIN. While monitoring the STATUS FLAG
(STA3) condition, adjust the “STLPF” adjustment data.
3. Adjustment range:
Adjustment bits:
±20%
6 bits
Align STLPF with the center of the STA3 = 1 (adjustment OK) condition range.
Adjustment point
Control data
"STLPF"
3F
0
1
0
Measurement data
STA3 "STLPF"
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SONY [ SONY CORPORATION ]
