CXA1616N/S
Pin No.
Symbol Pin voltage
Description
Equivalent circuit
SDIP SSOP
Connects a quasi-peak hold circuit
with a 33kΩ resistance and 0.22µF
capacitor to discriminate input signal
existence during composite sync input.
When there is a composite sync, the
voltage is held by the quasi-peak hold
circuit at 4.2 to 4.8V. This voltage is
then compared to a 3.8V reference
voltage, and an input signal is judged
to exist.
VCC
6
200
20k
8k
1k
1k
6
EHC
6
3.0, 4.8V
3.8V
30µA
12k
16k
The voltage is 3.0V when no input
signal exists.
Inputs the sync-on video (sync is
negative polarity). Connect a 0.47µF
capacitor and a 270Ω resistance in
series between the pin and its signal
source.
The slice level is determined by the
relationship between the sync
frequency and Pulse width and the
sum of the 200Ω internal resistance
and the 270Ω external resistance
multiplied by the 29µA current.
∆V ≈ 29µA × (T2/T1) × (200 + 270)
VCC
8.3V
4k
5.8V
7
VIDEO IN
4.5V
7
200
7
16k
72k
29µA
∆V
T1
T2
4.5V
Selects whether or not to output the
VD interval portion of HD (H Drive
Pulse).
Input is at TTL Ievel.
V Low ≤ 0.5V
200k
1k
70k
8
HD SEL
—
8
8
V High ≥ 2.0V
Low level: The VD interval HD is not
output.
High level or open: The VD interval HD
is output as is.
VCC
Connect a desired capacitor and a
12kΩ resistance in parallel to GND.
This capacitor changes the output
pulse width of clamp pulse.
(See Fig. 1)
10k
100
9
TIMING
10.5V
9
9
1k
17k
30µA
– 4 –
SONY [ SONY CORPORATION ]
