CXA1616N/S
Pin Description
(Ta = 25°C, VCC = 12V)
Description
Pin No.
Symbol Pin voltage
Equivalent circuit
SDIP SSOP
VCC
Inputs the vertical separate sync.
Inputs at TTL level and polarity is
positive/negative.
V Low ≤ 0.5V
V High ≥ 4.5V
Connect a pull-down resistance of
470kΩ or less to GND.
200k
1
1
VS IN
—
1k
8k
8k
1
20k
VCC
Connection pin of an integral capacitor
for the polarity discriminator circuit
(Polarity Check); connects a 0.22µF
capacitor to GND.
When the capacitor is connected at
positive polarity: 3.4V;
48k
32k
2
5
2
5
PVC
PHC
96k
1k
0.3, 3.4V
2
8k
negative polarity: 0.3V.
No input : 3.7V.
32k
Vertical ramp waveform generator.
Generates a ramp waveform
synchronized to the input separate
sync frequency. Connects a 0.68µF
capacitor to GND.
The charging time constant (rising
edge) of ramp waveform is determined
by the 2kΩ resistance and the external
0.68µF capacitor, and the discharging
time constant (falling edge) by the
external 0.68µF capacitor and the
internal 17µA current.
VCC
5V
48k
2k
3
3
EVC
4.3 to 7.9V
3
8k
32k
When there is a verticai separate
sync, the voltage at Pin 3 rises
between 5.5 and 7.9V, existence
discrimination (Exist Check) is
performed, and an input signal is
judged to exist.
17µA
The voltage is 4.3V when no input
signal exists.
VCC
72k
2k
100µA
Inputs the composite and horizontal
separate sync (positive/negative
polarity). Amplitude is 1 to 5Vp-p. Input
through a capacitor.
200
4
4
CS IN
4.2V
4
400k
4V
– 3 –
SONY [ SONY CORPORATION ]
