CXA1616N/S
(Ta = 25°C, VCC = 12V, See the Electrical Characteristics Test Circuit)
Measure-
Max. Unit
Symbol
Min.
Typ.
No.
Item
Measurement description
ment point
The voltage integral of the vertical
polarity discrimination circuit for
VS (vertical separate sync) input.
Input signal F (negative logic).
PVC
(Pin 2)
11 PVC voltage 1 VPV1
12 PVC voltage 2 VPV2
13 PHC voltage 1 VPH1
14 PHC voltage 2 VPH2
15 EVC voltage 1 VEV1
16 EVC voltage 2 VEV2
17 EHC voltage 1 VEH1
18 EHC voltage 2 VEH2
—
0.3
—
—
—
—
—
—
—
—
V
V
V
V
V
V
V
V
The voltage integral of the vertical
polarity discrimination circuit for
VS (vertical separate sync) input.
Input signal G (positive Iogic).
PVC
(Pin 2)
—
—
—
—
—
—
—
3.4
0.4
3.4
7.9
4.3
4.8
3.0
The voltage integral of the vertical
polarity discrimination circuit for
CS (composite sync) input.
PHC
(Pin 5)
Input signal H (negative logic).
The voltage integral of the vertical
polarity discrimination circuit for
CS (composite sync) input.
PHC
(Pin 5)
Input signal I (positive logic).
Measures the voltage of the vertical
ramp waveform generator for
VS (vertical separate sync) input.
Input signal A.
EVC
(Pin 3)
Measures the voltage of the vertical
ramp waveform generator for
VS (vertical separate sync) input.
No input signal.
EVC
(Pin 3)
Measurers the sync existence
discrimination voltage for
CS (composite sync) input.
Input signal J.
EHC
(Pin 6)
Measures the sync existence
discrimination voltage for
CS (composite sync) input.
No input signal.
EHC
(Pin 6)
Measures the delay difference
between CS and HD for
CS (composite sync) Input. The
time from the CS (negative polarity)
fall time (50%) to the HD output
rise time (50%). Input signal B.
HD
Pin 18
Pin 20
19 HD delay 1
td1
td2
120
120
190
205
250
260
ns
ns
(
(
(
(
Measures the delay difference
between CS and HD for
CS (composite sync) input. The
time from the CS (positive polarity)
rise time (50%) to the HD output
rise time (50%). Input signal D.
HD
Pin 18
Pin 20
20 HD delay 2
– 8 –
SONY [ SONY CORPORATION ]
