SNAD02C
8-CHANNEL 10-BIT ADC
6. Functional Descriptions
VDD
Host CPU
SNAD02
VDD
AVDD
REF
START
Output Port1
START
CLK
CLK
Output Port2
DIO
I/O port
DIO
0.1uF
VSS
AVSS
CH[0]
CH[1]
Analog/Digital
Signal
CH[7]
Figure-2 Interface with Host CPU
6.1. Interface Format
START
CLK
Channel Setting
HiZ
CM2
CM1
CM1
CM0
CM0
CH[7] CH[6] CH[5]
CH[4] CH[3] CH[2] CH[1] CH[0]
X
X
X
X
X
X
X
X
X
X
DIO
Port Input
Control Register Setting
HiZ
CM2
PH
PL
RF
MB
X
X
X
X
DIO
Port Input
Digital Input Reading
HiZ
CM2
CM1
CM0
CM0
DI[7] DI[6]
DI[5]
PDS
DI[4]
PDS
DI[3]
PDS
DI[2]
DI[1]
DI[0] DI[7]
DI[6]
PDS
DI[5] DI[4]
DI[3]
PDS
DIO
Port Input
Port Output
Power Down
HiZ
CM2
CM1
PDS
PDS
PDS
PDS
PDS
PDS
PDS
PDS
DIO
Port Input
Port Output
Figure-3 Timing Diagram of Whole Commands
Version: 1.3
July 31, 2003
5
SONIX [ SONIX TECHNOLOGY COMPANY ]
