SNAD02C
8-CHANNEL 10-BIT ADC
(1) Command ID: (100)
(2) 3-bit channel number data behind command ID.
(3) The analog signal of the selected channel is sampled to ADC. ADC refers the reference
voltage and converts the sampled analog signal to digital domain by successive-
approximation method.
(4) The 10-bit output data (result of conversion) of ADC is sent to DIO port from MSB and is
triggered by CLK. The maximum clock frequency is 500kHz @ 2.7v. (Maximum conversion
rate=25KHz)
(5) After the 10-bits ADC data has been sent out, if the START is kept in LOW and CLK is kept in
High/Low transition, then the data with uncertain value are kept appearing on DIO. These
data can just be ignored.
Channel ID[2:0]
Selected Channel
000
001
010
011
100
101
110
111
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
Table-4 Channel Selection Table
6.5. Timing of Digital Input Reading
START
CLK
Digital Input
Reading
HiZ
CM
2
CM
1
DI[3] DI[2] DI[1]
DI[6] DI[5] DI[4] DI[3]
CM0 DI[7] DI[6] DI[5] DI[4]
DI[0] DI[7]
DIO
Port Input
Port Output
Figure-7 The timing diagram of the digital input reading
Version: 1.3
July 31, 2003
9
SONIX [ SONIX TECHNOLOGY COMPANY ]
