SNAD02C
8-CHANNEL 10-BIT ADC
AMENDMENT HISTORY
Version
Ver 1.1
Ver 1.2
Date
February 12, 2003 First issue.
Description
March 18, 2003 Page3: wording modification in FEATURES list
Page8: modify Table-3 control register setting
Page10: modify Figure-10
Page11: “enters into power down mode at the 8th clock cycle”
Page11: more descript about power-down mode setting
Ver 1.3
July 31, 2003
1. Add version code “C” of chip no.
2. Page23: MB=1
3. This spec is modified form SNAD02_V1.2
Note:
This document is used to identify the different version “B” & “C” of SNAD01, the
most important is standby current and power down setting between version “B” &
“C”. For the detail please refer to related section.
Version: 1.3
July 31, 2003
2