5th Generation Hi-Speed USB Flash Media and CIR Controller with Integrated Card Power FETs
Datasheet
Chapter 6 Pin Descriptions
This section provides a detailed description of each signal. The signals are arranged in functional
groups according to their associated interface.
The “n” symbol in the signal name indicates that the active, or asserted state occurs when the signal
is at a low voltage level. When “n” is not present before the signal name, the signal is asserted when
at the high voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working
with a mixture of “active low” and “active high” signal. The term assert, or assertion indicates that a
signal is active, independent of whether that level is represented by a high or low voltage. The term
negate, or negation indicates that a signal is inactive.
6.1
PIN Descriptions
Table 6.1 USB2231/USB2232 Pin Descriptions
BUFFER
TYPE
NAME
SYMBOL
DESCRIPTION
CompactFlash (In True IDE mode) INTERFACE
CF Chip Select 1
CF Chip Select 0
CF_nCS1
O8PU
O8PU
O8
This pin is the active low chip select 1 signal for the CF
ATA device
CF_nCS0
CF_SA2
CF_SA1
CF_SA0
CF_IRQ
This pin is the active low chip select 0 signal for the task
file registers of CF ATA device in the True IDE mode.
CF Register
Address 2
This pin is the register select address bit 2 for the CF
ATA device.
CF Register
Address 1
O8
This pin is the register select address bit 1 for the CF
ATA device
CF Register
Address 0
O8
This pin is the register select address bit 0 for the CF
ATA device.
CF Interrupt
IPD
This is the active high interrupt request signal from the
CF device.
CF
CF_D[15:8]
I/O8PD
The bi-directional data signals CF_D15-CF_D8 in True
IDE mode data transfer.
Data 15-8
In the True IDE Mode, all of task file register operation
occur on the CF_D[7:0], while the data transfer is on
CF_D[15:0].
The bi-directional data signal has an internal weak pull-
down resistor.
CF
CF_D[7:0]
I/O8PD
IPU
The bi-directional data signals CF_D7-CF_D0 in the
True IDE mode data transfer.
Data7-0
In the True IDE Mode, all of task file register operation
occur on the CF_D[7:0], while the data transfer is on
CF_D[15:0].
The bi-directional data signal has an internal weak pull-
down resistor.
IO Ready
CF_IORDY
This pin is active high input signal.
This pin has an internally controlled weak pull-up
resistor.
SMSC USB2231/USB2232
Revision 1.3 (07-12-05)
DATA1S3HEET
SMSC [ SMSC CORPORATION ]
