9.3.1 PARALLEL PORT EPP TIMING
t18
t9
AX
SD<7:0>
t17
t8
t12
t19
nIOW
t10
t11
IOCHRDY
t13
t20
t2
t5
nWRITE
t1
PD<7:0>
t16
t3
t14
t4
nDATAST
nADDRSTB
t15
t6
t7
nWAIT
Parameter
min
max
units
Notes
t1
t2
nIOW Asserted to PDATA Valid
nWAIT Asserted to nWRITE Change
nWRITE to Command Asserted
nWAIT Deasserted to Command Deasserted
nWAIT Asserted to PDATA Invalid
Time Out
Command Deasserted to nWAIT Asserted
SDATA Valid to IOW Asserted
nIOW Deasserted to DATA Invalid
nIOW Asserted to IOCHRDY Asserted
WAIT Deasserted to nIOCHRDY Deasserted
IOCHRDY Deasserted to nIOW Deasserted
nIOW Asserted to nWRITE Asserted
nWAIT Asserted to Command Asserted
Command Asserted to nWAIT Deasserted
PDATA Valid to Command Asserted
Ax Valid to nIOW Asserted
0
60
5
50
185
35
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
1
t3
t4
60
0
190
1
1
t5
t6
10
0
12
t7
t8
10
0
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
0
24
160
60
10
0
1
1
70
210
10
60
0
10
40
10
40
60
nIOW Deasserted to Ax Invalid
nIOW Deasserted to nIOW or nIOR Asserted
nWAIT Asserted to nWRITE Asserted
185
1
NOTE: WAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is considered to have settled
after it does not transition for a minimum of 50 nsec.
FIGURE 9 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE
SMSC DS – SP37E760
Page 67
Rev. 04/13/2001
SMSC [ SMSC CORPORATION ]
