t20
t12
AX
t15
t22
t19
t11
nIOR
t13
SD<7:0>
t8
t3
t10
IOCHRDY
nWRITE
t4
t5
PD<7:0>
t23
nDATASTB
t2
nADDRSTB
t21
nWAIT
Parameter
min
max
units
Notes
nIOR Deasserted to Command Deasserted
nWAIT Asserted to IOCHRDY Deasserted
Command Deasserted to PDATA Hi-Z
Command Asserted to PDATA Valid
nIOR Asserted to IOCHRDY Asserted
nWAIT Deasserted to nIOCHRDY Deasserted
nIOCHRDY Deasserted to nIOR Deasserted
nIOR Deasserted to SDATA High-Z (Hold Time)
PData Valid to SDATA Valid
t2
50
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
t3
0
0
0
t4
t5
t8
24
50
t10
t11
t12
t13
t15
t19
t20
t21
t22
t23
0
0
40
40
12
Time Out
10
40
10
0
Ax Valid to nIOR Asserted
nIOR Deasserted to Ax Invalid
Command Deasserted to nWAIT Deasserted
nIOR Deasserted to nIOW or nIOR Asserted
nIOR Asserted to Command Asserted
40
55
NOTE:
1. nWRITE is controlled by setting the PDIR bit to "1" in the control register before
performing an EPP Read.
FIGURE 13 - EPP 1.7 DATA OR ADDRESS READ CYCLE
9.3.2 PARALLEL PORT ECP TIMING
9.3.2.1
Parallel Port FIFO (Mode 101)
The standard parallel port is run at or near the peak 500 Kbps allowed in the forward direction using DMA. The state
machine does not examine nAck and begins the next transfer based on Busy. Refer to FIGURE 14.
9.3.2.2
ECP Parallel Port Timing
The timing is designed to allow operation at approximately 2.0Mbytes/sec over a 15ft cable. If a shorter cable is used
then the bandwidth will increase.
9.3.2.3
Forward-Idle
When the host has no data to send it keeps HostClk (nStrobe) high and the peripheral will leave PeriphClk (Busy)
low.
SMSC DS – SP37E760
Page 71
Rev. 04/13/2001
SMSC [ SMSC CORPORATION ]
