t18
t9
AX
SD<7:0>
t17
t8
t6
nIOW
t12
t19
t10
t20
IOCHRDY
nWRITE
t11
t13
t1
t2
t5
PD<7:0>
t16
t3
nDATAST
t4
nADDRSTB
nWAIT
t21
Parameter
nIOW Asserted to PDATA Valid
min
max
units
Notes
t1
t2
0
0
5
50
40
35
50
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
Command Dessserted to nWRITE Change
nWRITE to Command
t3
t4
nIOW Deasserted to Command Deasserted
Command Deasserted to PDATA Invalid
Time Out
2
t5
50
10
10
0
t6
12
t8
SDATA Valid to nIOW Asserted
t9
nIOW Deasserted to DATA Invalid
nIOW Asserted to IOCHRDY Asserted
nWAIT Deasserted to IOCHRDY Deasserted
IOCHRDY Deasserted to nIOW Deasserted
nIOW Asserted to nWRITE Asserted
PDATA Valid to Command Asserted
Ax Valid to nIOW Asserted
t10
t11
t12
t13
t16
t17
t18
t19
t20
t21
0
24
40
10
0
10
40
10
100
50
35
nIOW Deasserted to Ax Invalid
nIOW Deasserted to nIOW or nIOR Asserted
nWAIT Asserted to IOCHRDY Deasserted
Command Deasserted to nWAIT Deasserted
45
0
NOTES:
1. WRITE is controlled by clearing the PDIR bit to "0" in the control register before
performing an EPP Write.
2. This number is only valid if WAIT is active when nIOW goes active.
FIGURE 12 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE
SMSC DS – SP37E760
Page 70
Rev. 04/13/2001
SMSC [ SMSC CORPORATION ]
