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SP37E760 参数 Datasheet PDF下载

SP37E760图片预览
型号: SP37E760
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3 V的I / O控制器的嵌入式应用 [3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS]
分类和应用: 控制器
文件页数/大小: 78 页 / 507 K
品牌: SMSC [ SMSC CORPORATION ]
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5.4.4.9  
ecr (Extended Control Register)  
ADDRESS OFFSET = 402H  
Mode = all  
This register controls the extended ECP parallel port functions (Table 20).  
5.4.4.9.1  
BITS 7,6,5  
These bits are Read/Write and select the Mode.  
BIT 4 nErrIntrEn  
Read/Write (Valid only in ECP Mode)  
1: Disables the interrupt generated on the asserting edge of nFault.  
0: Enables an interrupt pulse on the high to low edge of nFault. Note that an interrupt will be generated if nFault is  
asserted (interrupting) and this bit is written from a “1” to a “0”. This prevents interrupts from being lost in the time  
between the read of the ecr and the write of the ecr.  
5.4.4.9.2  
BIT 3 dmaEn  
Read/Write  
1: Enables DMA (DMA starts when serviceIntr is “0”).  
0: Disables DMA unconditionally.  
5.4.4.9.3  
BIT 2 serviceIntr  
Read/Write  
1: Disables DMA and all of the service interrupts.  
0: Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has occurred serviceIntr bit  
shall be set to a “1” by hardware, it must be reset to “0” to re-enable the interrupts. Writing this bit to a “1” will not  
cause an interrupt.  
case dmaEn=1:  
During DMA (this bit is set to a “1” when terminal count is reached).  
case dmaEn=0 direction=0:  
This bit shall be set to “1” whenever there are writeIntrThreshold or more bytes free in the FIFO.  
case dmaEn=0 direction=1:  
This bit shall be set to “1” whenever there are readIntrThreshold or more valid bytes to be read from the FIFO.  
5.4.4.9.4  
BIT 1 full  
Read only  
1: The FIFO cannot accept another byte or the FIFO is completely full.  
0: The FIFO has at least 1 free byte.  
5.4.4.9.5  
BIT 0 empty  
Read only  
1: The FIFO is completely empty.  
0: The FIFO contains at least 1 byte of data.  
Table 20 - Extended Control Register  
MODE  
R/W  
000: Standard Parallel Port mode . In this mode the FIFO is reset and common collector drivers are  
used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will  
not tri-state the output drivers in this mode.  
001: PS/2 Parallel Port mode. Same as above except that direction may be used to tri-state the  
data lines and reading the data register returns the value on the data lines and not the value in  
the data register. All drivers have active pull-ups (push-pull).  
010: Parallel Port FIFO mode. This is the same as 000 except that bytes are written or DMAed to  
the FIFO. FIFO data is automatically transmitted using the standard parallel port protocol. Note  
that this mode is only useful when direction is 0. All drivers have active pull-ups (push-pull).  
SMSC DS – SP37E760  
Page 38  
Rev. 04/13/2001  
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