Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
11.2 Chip Level (Global) Control/Configuration Registers[0x00-0x2F]
The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of
the ADDRESS Port for register selection. All unimplemented registers and bits ignore writes and return
zero when read.
The INDEX PORT is used to select a configuration register in the chip. The DATA PORT is then used to
access the selected register. These registers are accessible only in the Configuration Mode.
Table 11.3 – Chip Level Registers
REGISTER
ADDRESS
CHIP (GLOBAL) CONTROL REGISTERS
DESCRIPTION
0x00 -
0x01
Reserved - Writes are ignored, reads return 0.
Config Control
0x02 W
The hardware automatically clears this bit after the
write, there is no need for software to clear the bit.
Bit 0 = 1: Soft Reset.
Bits 7:1 Reserved
Default = 0x00
on VCC POR,
VTR POR and
HARD RESET
Refer to the “Configuration Registers” table for the
soft reset value for each register.
0x03 - 0x06 Reserved - Writes are ignored, reads return 0.
Logical Device #
0x07 R/W A write to this register selects the current logical
device. This allows access to the control and
configuration registers for each logical device.
Note: The Activate command operates only on the
selected logical device.
Default = 0x00
on VCC POR,
VTR POR,
SOFT RESET and
HARD RESET
Card Level
Reserved
0x08 - 0x1F Reserved - Writes are ignored, reads return 0.
CHIP LEVEL, SMSC DEFINED
Device ID
0x20 R
A read only register which provides device
identification. Bits[7:0] = 0x74 when read.
Hard wired = 0x74
Device Rev
0x21 R
A read only register which provides device revision
information. Bits[7:0] = current revision when read.
Hard wired
= Current Revision
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
174
SMSC LPC47M182
DATASHEET
SMSC [ SMSC CORPORATION ]
