Table 33 − Parallel Port Connector
HOST
CONNECTOR
PIN NUMBER
STANDARD
nSTROBE
EPP
ECP
1
83
68-75
80
nWrite
nStrobe
2-9
10
11
12
PD<0:7>
nACK
BUSY
PE
PData<0:7>
Intr
PData<0:7>
nAck
79
nWait
Busy, PeriphAck(3)
PError,
78
(User Defined)
nAckReverse(3)
Select
13
14
77
82
SLCT
nALF
(User Defined)
NDatastb
nAutoFd,
HostAck(3)
nFault(1)
15
16
17
81
66
67
nERROR
nINIT
(User Defined)
nRESET
nPeriphRequest(3)
nInit(1)
nReverseRqst(3)
nSelectIn(1,3)
nSLCTIN
NAddrstrb
(1) = Compatible Mode
(3) = High Speed Mode
Note: For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the
IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. This document is available
from Microsoft.
6.7.1 IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES
Data Port
ADDRESS OFFSET = 00H
The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by
RESET. During a WRITE operation, the Data Register latches the contents of the internal data bus. The contents of
this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation in SPP mode,
PD0 - PD7 ports are buffered (not latched) and output to the host CPU.
Status Port
ADDRESS OFFSET = 01H
The Status Port is located at an offset of '01H' from the base address. The contents of this register are latched for the
duration of a read cycle. The bits of the Status Port are defined as follows:
BIT 0 TMOUT - TIME OUT
This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A logic O means
that no time out error has occurred; a logic 1 means that a time out error has been detected. This bit is cleared by a
RESET. Writing a one to this bit clears the time out status bit. On a write, this bit is self clearing and does not require a
write of a zero. Writing a zero to this bit has no effect.
BITS 1, 2 - are not implemented as register bits, during a read of the Printer Status Register these bits are a low level.
BIT 3 nERR - nERROR
The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic 0 means an error has
been detected; a logic 1 means no error has been detected.
BIT 4 SLCT - PRINTER SELECTED STATUS
The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic 1 means the printer is on
line; a logic 0 means it is not selected.
SMSC DS – LPC47S45x
Page 78 of 259
Rev. 07/09/2001
DATASHEET
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