Table 44A - Extended Control Register
MODE
R/W
000: Standard Parallel Port Mode . In this mode the FIFO is reset and common collector drivers are
used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will
not tri-state the output drivers in this mode.
001: PS/2 Parallel Port Mode. Same as above except that direction may be used to tri-state the
data lines and reading the data register returns the value on the data lines and not the value in
the data register. All drivers have active pull-ups (push-pull).
010: Parallel Port FIFO Mode. This is the same as 000 except that bytes are written or DMAed to the
FIFO. FIFO data is automatically transmitted using the standard parallel port protocol. Note that
this mode is only useful when direction is 0. All drivers have active pull-ups (push-pull).
011: ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the ecpDFifo
and bytes written to the ecpAFifo are placed in a single FIFO and transmitted automatically to
the peripheral using ECP Protocol. In the reverse direction (direction is 1) bytes are moved
from the ECP parallel port and packed into bytes in the ecpDFifo. All drivers have active
pull-ups (push-pull).
100: Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in
configuration register L3-CRF0. All drivers have active pull-ups (push-pull).
101: Reserved
110: Test Mode. In this mode the FIFO may be written and read, but the data will not be transmitted
on the parallel port. All drivers have active pull-ups (push-pull).
111: Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and
0x401. All drivers have active pull-ups (push-pull).
Table 44B
CONFIG REG B
Table 44C
CONFIG REG B
IRQ SELECTED
BITS 5:3
DMA
BITS 2:0
SELECTED
15
14
11
10
9
7
5
110
101
100
011
010
001
111
000
3
2
1
011
010
001
000
All Others
All Others
OPERATION
Mode Switching/Software Control
Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control
(mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the
ECP port only in the data transfer phase (modes 011 or 010).
Setting the mode to 011 or 010 will cause the hardware to initiate data transfer.
If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be
switched into mode 000 or 001. The direction can only be changed in mode 001.
Once in an extended forward mode the software should wait for the FIFO to be empty before switching back to mode
000 or 001. In this case all control signals will be deasserted before the mode switch. In an ecp reverse mode the
software waits for all the data to be read from the FIFO before changing back to mode 000 or 001. Since the automatic
hardware ecp reverse handshake only cares about the state of the FIFO it may have acquired extra data which will be
discarded. It may in fact be in the middle of a transfer when the mode is changed back to 000 or 001. In this case the
port will deassert nAutoFd independent of the state of the transfer. The design shall not cause glitches on the
handshake signals if the software meets the constraints above.
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