BLOCK DIAGRAM
FAN_TACH1*
FAN_TACH2*
FAN1*
Game Port Signals*
(1-Dual)
FAN2*
nIO_SMI nIO_PME
SMI PME
...
Fan
Control
Game Port
PD0-7
MULTI-MODE
PARALLEL
PORT
MUX
BUSY, SLCT, PE,
nERROR, nACK
DATA BUS
nSTB, nSLCTIN,
nINIT, nALF
SER_IRQ
PCI_CLK
SERIAL
IRQ
GP1[0:7]*
GP2[0:2,4:7]*
GP3[0:7]*, GP4[0:3]*
GP5[0:7]*, GP6[0:1]*
GENERAL
PURPOSE
I/O
ADDRESS BUS
CONFIGURATION
REGISTERS
ACPI
BLOCK
TXD1, nCTS1, nRTS1
RXD1
16C550
COMPATIBLE
SERIAL
PORT 1
nDSR1, nDCD1, nRI1, nDTR1
LPC Bus
Signals
LPC BUS
INTERFACE
CONTROL BUS
IRRX2, IRTX2
16C550
COMPATIBLE
SERIAL
TXD2(IRTX), nCTS2, nRTS2
*
WDATA
RXD2(IRRX) *
PORT 2 WITH
WCLOCK
INFRARED
nDSR2, nDCD2, nRI2, nDTR2
*
SMSC
PROPRIETARY
82077
COMPATIBLE
VERTICAL
DIGITAL
DATA
SEPARATOR
WITH WRITE
PRECOM-
MPU-401
SERIAL
PORT
MIDI_IN
FLOPPYDISK
CONTROLLER
MIDI_OUT
PENSATION
CORE
RCLOCK
RDATA
KCLK
KDATA
MCLK
MDATA
8042
CLOCK
GEN
GATEA20, KRESET
DENSEL
nINDEX
nTRK0
nDS0
nDIR
nMTR0
nRDATA
nWDATA
nDSKCHG
nWRPRT
nWGATE
nSTEP DRVDEN0
VTR Vcc Vss
*
DRVDEN1
*
nHDSEL
CLK32 CLOCKI
32KHz 14MHz
Denotes Multifunction Pins
FIGURE 1 – LPC47M10x BLOCK DIAGRAM
REFERENCE DOCUMENTS
1. SMSC Consumer Infrared Communications Controller (CIrCC) V1.X
2. IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993.
3. Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook.
4. PCI Bus Power Management Interface Specification, Rev. 1.0, Draft, March 18, 1997.
5. Low Pin Count (LPC) Interface Specification, Revision 1.0, September 29, 1997, Intel Document.
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SMSC [ SMSC CORPORATION ]
