DESCRIPTION OF PIN FUNCTIONS
PIN
No./
QFP
BUFFER
TYPE
PER
BUFFER
TYPE
NAME
TOTAL
SYMBOL
NOTES
FUNCTION
(NOTE 1)
47
50
48
49
17
General Purpose I/O
/MIDI_OUT
General Purpose I/O
/SMI Output
General Purpose I/O /
LED
General Purpose I/O /
LED
1
1
1
1
1
GP26
/MIDI_OUT
GP27
/nIO_SMI
IO12
IO12
(I/O12/OD12)/
O12
(I/O12/OD12)/
OD12
GP60 /LED1 IO12
(I/O12/OD12)/
O12
(I/O12/OD12)/
O12
(I/O12/OD12)/
OD12
10
10
GP61 /LED2 IO12
General Purpose I/O /
Power Management
Event
GP42
/nIO_PME
IO12
28
General Purpose I/O
/Device Disable Reg.
Control
1
GP43/DDRC IO8
(I/O8/OD8)/I
Note:
The "n" as the first letter of a signal name indicates an "Active Low" signal.
Note 1: Buffer types per function on multiplexed pins are separated by a slash “/”. Buffer types in parenthesis
represent multiple buffer types for a single pin function.
Note 2: The nLPCPD pin may be tied high. The LPC interface will function properly if the nPCI_RESET signal
follows the protocol defined for the nLRESET signal in the “Low Pin Count Interface Specification”.
Note 3: If the 32kHz input clock is not used the CLKI32 pin must be grounded. There is a bit in the configuration
register at 0xF0 in Logical Device A that indicates whether or not the 32kHz clock is connected. This bit
determines the clock source for the fan tachometer, LED and “wake on specific key” logic. Set this bit to ‘1’
if the clock is not connected.
Note 4. The fan control pins (FAN1 and FAN2) come up as outputs and low following a VCC POR and Hard Reset.
These pins revert to their non-inverting GPIO output function when VCC is removed from the part.
Note 5: The IRTX pins (IRTX2/GP35 and GP53/TXD2 (IRTX)) are driven low when the part is powered by VTR
(VCC=0V with VTR=3.3V). These pins will remain low following a power-up (VCC POR) until serial port 2 is
enabled by setting the activate bit, at which time the pin will reflect the state of the transmit output of the
Serial Port 2 block.
Note 6:The VCC power-up default for this pin is Logic “0” if the IRTX function is programmed on the GPIO.
Note 7: VTR can be connected to VCC if no wakeup functionality is required.
Note 8: The GP24 /SYSOPT pin requires an external pulldown resistor to put the base IO address for configuration
at 0x02E. An external pullup resistor is required to move the base IO address for configuration to 0x04E.
Note 9: External pullups must be placed on the nKBDRST and A20M pins. These pins are GPIOs that are inputs
after an initial power-up (VTR POR). If the nKBDRST and A20M functions are to be used, the system must
ensure that these pins are high. See Section “Pins That Require External Pullup Resistor”.
Note 10: The LED pins are powered by VTR so that the LEDs can be controlled when the part is under VTR power
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