Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
13.1
System Control and Status Registers
The System CSR’s are directly addressable memory mapped registers with a base address offset
2
range of 050h to 2DCh. These registers are accessed through the I C/SPI serial interfaces or the
MIIM/SMI serial interface. For more information on the various LAN9313/LAN9313i modes and their
corresponding address configurations, see Section 2.3, "Modes of Operation," on page 23.
Table 13.1 lists the System CSR’s and their corresponding addresses in order. All system CSR’s are
reset to their default value on the assertion of a chip-level reset.
The System CSR’s can be divided into 8 sub-categories. Each of these sub-categories contains the
System CSR descriptions of the associated registers. The register descriptions are categorized as
follows:
Section 13.1.1, "Interrupts," on page 151
Section 13.1.2, "GPIO/LED," on page 155
Section 13.1.3, "EEPROM," on page 160
Section 13.1.4, "IEEE 1588," on page 164
Section 13.1.5, "Switch Fabric," on page 192
Section 13.1.6, "PHY Management Interface (PMI)," on page 207
Section 13.1.7, "Virtual PHY," on page 209
Section 13.1.8, "Miscellaneous," on page 224
Table 13.1 System Control and Status Registers
ADDRESS
OFFSET
SYMBOL
REGISTER NAME
RESERVED
ID_REV
000h - 04Ch
050h
Reserved for Future Use
Chip ID and Revision Register, Section 13.1.8.1
Interrupt Configuration Register, Section 13.1.1.1
Interrupt Status Register, Section 13.1.1.2
Interrupt Enable Register, Section 13.1.1.3
Reserved for Future Use
IRQ_CFG
INT_STS
054h
058h
INT_EN
05Ch
RESERVED
BYTE_TEST
RESERVED
HW_CFG
060h
064h
Byte Order Test Register, Section 13.1.8.2
Reserved for Future Use
068h - 070h
074h
Hardware Configuration Register, Section 13.1.8.3
Reserved for Future Use
RESERVED
GPT_CFG
078h - 088h
08Ch
General Purpose Timer Configuration Register,
Section 13.1.8.4
GPT_CNT
RESERVED
FREE_RUN
RESERVED
PMI_DATA
090h
094h - 098h
09Ch
General Purpose Timer Count Register, Section 13.1.8.5
Reserved for Future Use
Free Running Counter Register, Section 13.1.8.6
Reserved for Future Use
0A0h
0A4h
PHY Management Interface Data Register,
Section 13.1.6.1
PMI_ACCESS
0A8h
PHY Management Interface Access Register,
Section 13.1.6.2
SMSC LAN9313/LAN9313i
147
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
