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LAN9215I-MT 参数 Datasheet PDF下载

LAN9215I-MT图片预览
型号: LAN9215I-MT
PDF下载: 下载PDF文件 查看货源
内容描述: 高效的单芯片10/100以太网控制器与HP Auto-MDIX的和工业温度支持 [Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support]
分类和应用: 外围集成电路数据传输控制器局域网以太网局域网(LAN)标准时钟
文件页数/大小: 134 页 / 1602 K
品牌: SMSC [ SMSC CORPORATION ]
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Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support  
Datasheet  
5.3.20  
MAC_CSR_CMD – MAC CSR Synchronizer Command Register  
Offset:  
A4h  
Size:  
32 bits  
This register is used to control the read and write operations with the MAC CSR’s  
BITS  
DESCRIPTION  
TYPE  
DEFAULT  
31  
CSR Busy. When a 1 is written into this bit, the read or write operation is  
performed to the specified MAC CSR. This bit will remain set until the  
operation is complete. In the case of a read this means that the host can  
read valid data from the data register. The MAC_CSR_CMD and  
MAC_CSR_DATA registers should not be modified until this bit is cleared.  
SC  
0
30  
R/nW. When set, this bit indicates that the host is requesting a read  
operation. When clear, the host is performing a write.  
R/W  
0
29-8  
7-0  
Reserved.  
RO  
-
CSR Address. The 8-bit value in this field selects which MAC CSR will be  
accessed with the read or write operation.  
R/W  
00h  
5.3.21  
MAC_CSR_DATA – MAC CSR Synchronizer Data Register  
Offset:  
A8h  
Size:  
32 bits  
This register is used in conjunction with the MAC_CSR_CMD register to perform read and write  
operations with the MAC CSR’s  
BITS  
DESCRIPTION  
TYPE  
DEFAULT  
31-0  
MAC CSR Data. Value read from or written to the MAC CSR’s.  
R/W  
00000000h  
Revision 1.5 (07-18-06)  
SMSC LAN9215I  
DATA9S2HEET