Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
5.3.16
GPT_CNT-General Purpose Timer Current Count Register
Offset:
90h
Size:
32 bits
This register reflects the current value of the GP Timer.
BITS
31-16
15-0
DESCRIPTION
TYPE
RO
DEFAULT
Reserved
-
General Purpose Timer Current Count (GPT_CNT). This 16-bit field
reflects the current value of the GP Timer.
RO
FFFFh
5.3.17
WORD SWAP—Word Swap Control
Offset:
98h
Size:
32 bits
This register controls how words from the host data bus are mapped to the CSRs and Data FIFOs
inside the LAN9215I. The LAN9215I always sends data from the Transmit Data FIFO to the network
so that the low order word is sent first, and always receives data from the network to the Receive Data
FIFO so that the low order word is received first.
BITS
DESCRIPTION
TYPE
DEFAULT
31:0
Word Swap. If this field is set to 00000000h, or anything except
R/W
NASR
00000000h
0xFFFFFFFFh, the LAN9215I maps words with address bit A[1]=1 to the
high order words of the CSRs and Data FIFOs, and words with address bit
A[1]=0 to the low order words of the CSRs and Data FIFOs. If this field is
set to 0xFFFFFFFFh, the LAN9215I maps words with address bit A[1]=1 to
the low order words of the CSRs and Data FIFOs, and words with address
bit A[1]=0 to the high order words of the CSRs and Data FIFOs.
Revision 1.5 (07-18-06)
SMSC LAN9215I
DATA9S0HEET
SMSC [ SMSC CORPORATION ]
