Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
5.3.14
GPIO_CFG—General Purpose IO Configuration Register
Offset:
88h
Size:
32 bits
This register configures the GPIO and LED functions.
BITS
DESCRIPTION
TYPE
DEFAULT
31
Reserved
RO
-
30:28
LED[3:1] enable (LEDx_EN). A ‘1’ sets the associated pin as an LED
output. When cleared low, the pin functions as a GPIO signal.
LED1/GPIO0 – bit 28
R/W
000
LED2/GPIO1 – bit 29
LED3/GPIO2 – bit 30
27
Reserved
RO
-
26:24
GPIO Interrupt Polarity 0-2 (GPIO_INT_POL). When set high, a high logic
level on the corresponding GPIO pin will set the corresponding INT_STS
register bit. When cleared low, a low logic level on the corresponding GPIO
pin will set the corresponding INT_STS register bit.
GPIO Interrupts must also be enabled in GPIOx_INT_EN in the INT_EN
register.
R/W
000
GPIO0 – bit 24
GPIO1 – bit 25
GPIO2 – bit 26
Note:
GPIO inputs must be active for greater than 40nS to be recognized
as interrupt inputs.
23
Reserved
RO
-
22:20
EEPROM Enable (EEPR_EN). The value of this field determines the
function of the external EEDIO and EECLK:
Please refer to Table 5.4 for the EEPROM Enable bit function definitions.
R/W
000
Note:
The host must not change the function of the EEDIO and EECLK
pins when an EEPROM read or write cycle is in progress. Do not
use reserved settings.
Note:
Regardless of whether the internal or external PHY is selected,
RX_DV, TX_CLK and RX_CLK reflect the signals on the internal
PHY and the MAC always drives TX_EN.
19
Reserved
RO
-
18:16
GPIO Buffer Type 0-2 (GPIOBUFn). When set, the output buffer for the
corresponding GPIO signal is configured as a push/pull driver. When
cleared, the corresponding GPIO set configured as an open-drain driver.
GPIO0 – bit 16
R/W
000
GPIO1 – bit 17
GPIO2 – bit 18
15:11
10:8
Reserved
RO
-
GPIO Direction 0-2 (GPDIRn). When set, enables the corresponding GPIO
as output. When cleared the GPIO is enabled as an input.
R/W
0000
GPIO0 – bit 8
GPIO1 – bit 9
GPIO2 – bit 10
7:5
Reserved
RO
-
Revision 1.5 (07-18-06)
SMSC LAN9215I
DATA8S8HEET
SMSC [ SMSC CORPORATION ]
