High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.5.4.26 Buffer Manager Interrupt Mask Register (BM_IMR)
Register #:
1C20h
Size:
32 bits
This register contains the Buffer Manager interrupt mask, which masks the interrupts in the Buffer
Manager Interrupt Pending Register (BM_IPR). All Buffer Manager interrupts are masked by setting
the Interrupt Mask bit. Clearing this bit will unmask the interrupts. Refer to Chapter 5, "System
Interrupts," on page 49 for more information.
BITS
DESCRIPTION
TYPE
DEFAULT
31:1
0
RESERVED
RO
-
Interrupt Mask
R/W
1b
When set, this bit masks interrupts from the Buffer Manager. The status bits
in the Buffer Manager Interrupt Pending Register (BM_IPR) are not affected.
Revision 1.2 (04-08-08)
438
SMSC LAN9312
DATASHEET
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