High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.5.4.3
Buffer Manager Flow Control Pause Level Register (BM_FC_PAUSE_LVL)
Register #:
1C02h
Size:
32 bits
This register configures the buffer usage level when a Pause frame or backpressure is sent.
BITS
DESCRIPTION
TYPE
DEFAULT
31:16
15:8
RESERVED
RO
-
Pause Level Low
R/W
21h
These bits specify the buffer usage level during times when 2 or 3 ports are
active.
Each buffer is 128 bytes.
Note:
A port is “active” when 36 buffers are in use for that port.
7:0
Pause Level High
R/W
3Ch
These bits specify the buffer usage level during times when 1 port is active.
Each buffer is 128 bytes.
Note:
A port is “active” when 36 buffers are in use for that port.
Revision 1.2 (04-08-08)
414
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
