High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Table 3.5 EEPROM Pins (continued)
BUFFER
PIN
NAME
SYMBOL
TYPE
DESCRIPTION
EEPROM
Microwire
Chip Select
EECS
O8
EEPROM Microwire Chip Select: In Microwire
EEPROM mode (EEPROM_TYPE = 0), this pin is
the Microwire EEPROM chip select output.
Note:
In I2C mode (EEPROM_TYPE=1), this pin
is not used and is driven low.
101
EEPROM_SIZE_0
EEPROM
Size Strap 0
IS
Note 3.3
EEPROM Size Strap 0: Configures the low bit of
the EEPROM size range as specified in Section
10.2, "I2C/Microwire Master EEPROM Controller,"
on page 137. See Note 3.4.
Note 3.3 The IS buffer type is valid only during the time specified in Section 15.5.2, "Reset and
Configuration Strap Timing," on page 445.
Note 3.4 Configuration strap values are latched on power-on reset or nRST de-assertion.
Configuration strap pins are identified by an underlined symbol name. Refer to Section
4.2.4, "Configuration Straps," on page 40 for more information.
Note 3.5 The IS buffer type is valid only during the time specified in Section 15.5.2, "Reset and
Configuration Strap Timing," on page 445 and when in I2C mode.
Table 3.6 Dedicated Configuration Strap Pins
BUFFER
PIN
NAME
SYMBOL
TYPE
DESCRIPTION
LED Enable
Strap
LED_EN
IS
(PU)
LED Enable Strap: Configures the default value
for the LED_EN bits in the LED Configuration
Register (LED_CFG). When latched low, all 8
LED/GPIO pins are configured as GPIOs. When
latched high, all 8 LED/GPIO pins are configured
as LEDs. See Note 3.6.
67
PHY_ADDR_SEL
PHY Address
Strap
IS
(PU)
PHY Address Select Strap: Configures the default
MII management address values for the PHYs
(Virtual, Port 1, and Port 2) as detailed in Section
7.1.1, "PHY Addressing," on page 82.
68
0
1
0
1
1
2
2
3
See Note 3.6.
Revision 1.2 (04-08-08)
SMSC LAN9312
DATA3S2HEET
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